Vertical design of InN field effect transistors

• Published in: 2010 Proceedings of the European Solid State Device Research Conference pp. 428 - 431
• Main Authors: Granzner, Ralf, Kittler, Mario, Schwierz, Frank, Polyakov, Vladimir M
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2010
• Subjects: Charge carrier processes; Electric potential; Gallium; Gallium nitride; Logic gates; Mathematical model; Transistors
• ISBN: 142446658X; 9781424466580
• ISSN: 1930-8876
• DOI: 10.1109/ESSDERC.2010.5618189

The vertical design of indium nitride field effect transistors is investigated by numerical simulation. To this end, the Schrödinger equations for electrons and holes and Poisson's equation are solved self-consistently. It is shown that in several layer sequences simultaneously two-dimensional electron and hole gases are formed in the InN channel. It is demonstrated that because of the high unintentional n-type doping only thin InN layers are useful for proper transistor operation. Strain in the InN layer leads to the formation of parasitic hole channels which can dramatically deteriorate transistor characteristics. Finally it is shown that thin relaxed InN channels on GaN or AlInN buffers are a viable option for InN transistors.