A new technique for high speed decimal logarithm computation of decimal floating-point number

• Published in: 14th International Conference on Computer and Information Technology (ICCIT 2011) pp. 208 - 212
• Main Authors: Khan, K. M. N. H., Ali, Md Liakot, Islam, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2011
• Subjects: Algorithm design and analysis; Convergence; Decimal logarithm; FPGA; Hardware; radix-10 floating-point arithmetic; VLSI
• ISBN: 1612849075; 9781612849072
• DOI: 10.1109/ICCITechn.2011.6164785

This paper presents a new design and a fast technique for implementation of a 32-bit decimal floating-point (DFP) logarithmic computation to efficiently calculate radix-10 logarithm of a decimal number. Conventional techniques first convert decimal inputs to binary, then perform base-2 logarithm operations, and finally results are converted back to decimal radix. It sometimes causes errors due to the back and forth conversions of the bases. The technique described in this paper uses a 32-bit floating-point arithmetic, and utilizes only addition and subtraction operations. It does not require any decimal to binary conversion, or division operation. As a result, the described algorithm offers a low-cost, hardware-efficient and lower power consumption method for computing decimal floating-point numbers.