FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)

• Published in: 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) pp. 5 pp. - 26
• Main Authors: Garcia-Martinez, M.A., Posada-Gomez, R., Morales-Luna, G., Rodriguez-Henriquez, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Arithmetic; Delay; Elliptic curve cryptography; Error correction codes; Field programmable gate arrays; Galois fields; Hardware; NIST; Signal processing; Software performance
• ISBN: 0769524567; 9780769524566
• ISSN: 2325-6532; 2640-0472
• DOI: 10.1109/RECONFIG.2005.18

Arithmetic operations over finite fields GF(2 m ) are widely used in cryptography, error-correcting codes and signal processing. In particular, multiplication is especially relevant since other arithmetic operators, such as division or exponentiation, which they usually utilize multipliers as building blocks. Hardware implementation of field multiplication may provide a great speedup in procedure's performance, which easily exceeds the one observed in software platforms. In this paper we deal with an FPGA implementation of an efficient serial multiplier over the binary extension fields GF(2 193 ) and GF(2 239 ). Those extension fields are included among the ones recommended by NIST (National Institute of Standards and Technology) standards for Elliptic Curve Cryptography. Our multiplier is of type Serial/Parallel LSB-first and operates with a latency of m-clock cycles, where m is the length of the field word. We calculate the space complexity attending the number of slices used in the FPGA