Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure

• Published in: 2010 IEEE International Interconnect Technology Conference pp. 1 - 3
• Main Authors: Yu Yang, Katti, Guruprasad, Labie, Riet, Travaly, Youssef, Verlinden, Bert, De Wolf, Ingrid
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2010
• Subjects: Circuit stability; Circuit testing; Integrated circuit measurements; MOS devices; MOSFETs; Residual stresses; Stacking; Thermal degradation; Thermal stability; Through-silicon vias
• ISBN: 1424476763; 9781424476763
• ISSN: 2380-632X; 2380-6338
• DOI: 10.1109/IITC.2010.5510710

Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without TSVs. The stability of this structure was investigated by thermal cycling tests. Measurements after 1000 cycles between -55 and 125°C demonstrated good robustness of the stacked integrated circuit (SIC) structure. Residual stress induced by the TSVs was experimentally examined by micro-Raman spectroscopy. The results revealed that TSV induced stress is negligible for carrier mobility in this technology.