Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer

• Published in: 2012 International Symposium on System on Chip (SoC) pp. 1 - 8
• Main Authors: Roth, C., Reder, S., Erdogan, G., Sander, O., Almeida, G. M., Bucher, H., Becker, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2012
• Subjects: Computational modeling; Computer architecture; Computers; Kernel; Receivers; Synchronization; Tiles
• ISBN: 1467328952; 9781467328951
• DOI: 10.1109/ISSoC.2012.6376364

The growing complexity of embedded applications currently causes a trend towards multi-core processors in the embedded domain. Time-consuming detailed simulations make the design of such systems increasingly sophisticated. In this work, applicability of Parallel Discrete Event Simulation (PDES) in the context of cycle-accurate Multi-Processor System-on-Chip (MPSoC) simulation is investigated on the Single-chip Cloud Computer (SCC) from Intel. The presented strategy targets asynchronous parallel model execution where only adjacent model partitions need to synchronize with each other in order to advance in simulation time. Performance of the approach is evaluated by means of a scalable cycle-accurate MPSoC model called HeMPS. For a 8×8 RTL model measurements reveal a speedup versus sequential RTL simulation of 25.3×. When exchanging RTL processing elements by cycle-accurate simulators a speedup of 56.3× versus sequential RTL simulation is obtained. These results promise good suitability of the asynchronous strategy for detailed parallel MPSoC simulation on an architecture like the SCC.