Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation

• Published in: 2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) pp. 166 - 170
• Main Authors: Islam, A.K.M. Mahfuzul, Shimizu, Ryota, Onodera, Hidetoshi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-03-2019
• Subjects: Delays; Integrated circuit modeling; Logic gates; Monte Carlo methods; MOSFET circuits; Semiconductor device measurement; Switches
• ISBN: 9781728114644; 1728114640
• ISSN: 1071-9032; 2158-1029
• DOI: 10.1109/ICMTS.2019.8730976

We present measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On- Thin-Buried-Oxide process. Measurement results reveal that the expected value of delay fluctuation decreases rapidly with the increase of logic depth. However, the delay fluctuation above 99th percentile is not strongly affected by logic depth. RTN-induced delay fluctuations are found to be not affected by the switching speed of logic gates. The measurement results provide useful insights into developing a statistical static timing analysis (SSTA) framework to asses the worst-case delay under the presence of RTN.