Managing application task mapping on multi-processor system-on-chip based IMS handsets Design methodology of MPSoC based IMS handsets as the system standards debate goes on

• Published in: 2007 International Conference on IP Multimedia Subsystem Architecture and Applications pp. 1 - 5
• Main Authors: Guha, D., Vinod, C.J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2007
• Subjects: Application software; application tasks; Computer architecture; Design methodology; IMS handsets; mapping; MPSoC; Multiprocessing systems; Software standards; Standards development; System-on-a-chip; Technology management; Telephone sets; Time to market
• ISBN: 9781424426713; 1424426715
• DOI: 10.1109/IMSAA.2007.4559080

Handset developers and system architecture solution providers have less prominence to standards and specifications development compared to operators and network infra vendors. There are marked lacks of agreed standards and consistent specifications that influence system architecture design for IMS-capable handsets. To ensure the capacity of convergence in IMS, as more and more applications need support on the handset, performance becomes an increasingly complex demand to satisfy for handset vendors. The problem is even more pronounced when a multi-processor system-on-chip (MPSoC) platform is considered, mainly because of application task mapping onto the MPSoC components and software verification. This paper discusses the situations of mapping application tasks to a heterogeneous MPSoC invoked through managing IMS profiles. It is intended to show a design methodology for MPSoC based IMS handsets as the standardization debate goes on, so that vendors may be poised to leverage upon futuristic market trends to provide the shortest time-to-market all-IMS handset with non-recurrent engineering designs.