Fault detection in VLSI circuits

• Published in: ICM'99. Proceedings. Eleventh International Conference on Microelectronics (IEEE Cat. No.99EX388) pp. 101 - 104
• Main Author: Shaer, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Algorithm design and analysis; Circuit analysis; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Partitioning algorithms; Sequential analysis; Sequential circuits; Very large scale integration
• ISBN: 9780780366435; 0780366433
• DOI: 10.1109/ICM.2000.884815

In this paper, an algorithm for fault detection in VLSI circuits is presented. This algorithm is based on partitioning combinational and sequential circuits for pseudo-exhaustive testing. The partitioning algorithm is based on an analysis of a circuit's primary input cones and fanout values. Once a circuit has been partitioned, its primary outputs and partitioned points are tested exhaustively. By exhaustively testing individual blocks, faults within these blocks are detected and located. The results show that the partitioning algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms. In addition, the algorithm is based upon pseudo-exhaustive testing methods where fault simulation is not required for test pattern generation and grading; hence, engineering design time and cost are further reduced.