FPGA implementation of block truncation coding algorithm for gray scale and color images

• Published in: CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436) Vol. 1; pp. 23 - 26 vol.1
• Main Authors: Saif, S.M., Nassar, S., Abbas, H.M., Soliman, A.T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Color; Field programmable gate arrays; Hardware; Image coding; Image processing; Image storage; Microprocessors; Pixel; Quantization; Video compression
• ISBN: 9780780377813; 0780377818
• ISSN: 0840-7789; 2576-7046
• DOI: 10.1109/CCECE.2003.1226335

This paper presents a field programmable gate array (FPGA) implementation for video compression using block truncation coding (BTC) image compression technique [E. Delp et al., 1979]. The implementation exploits the inherent parallelism of the BTC algorithm to provide efficient algorithm-to-architecture mapping. The implementation is shown for gray scale images and promoted to color ones. The Xilinx VirtexE BTC implementation has shown to provide about 23.4 /spl times/ 10/sup 6/ of pixels per second which is about 3500 times faster than an Intel Pentium III 550 MHz processor.