A comparative analysis of high-speed digital test techniques

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to higher clock frequencies and non availability/economical of VLSI testers. We outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. Various imp...

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Published in:	Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411) Vol. 1; pp. 379 - 384 vol.1
Main Authors:	Sachdev, M., Shashaani, M.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 1999
Subjects:	Circuit testing Clocks Costs Frequency Integrated circuit testing Logic testing Manufacturing Ring oscillators Timing Very large scale integration
Online Access:	Get full text
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Abstract	Testing of high performance integrated circuits is becoming increasingly a challenging task owing to higher clock frequencies and non availability/economical of VLSI testers. We outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. Various implementation aspects of this technique are also addressed.
AbstractList	Testing of high performance integrated circuits is becoming increasingly a challenging task owing to higher clock frequencies and non availability/economical of VLSI testers. We outline a DFT strategy such that high performance devices can be tested on relatively low performance testers. Various implementation aspects of this technique are also addressed.
Author	Sachdev, M. Shashaani, M.
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SubjectTerms	Circuit testing Clocks Costs Frequency Integrated circuit testing Logic testing Manufacturing Ring oscillators Timing Very large scale integration
Title	A comparative analysis of high-speed digital test techniques
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