A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit

• Published in: 1994 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 4; pp. 323 - 326 vol.4
• Main Authors: Kuo, J.B., Su, K.W., Lou, J.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1994
• Subjects: Adders; BiCMOS integrated circuits; Buildings; Clocks; CMOS logic circuits; CMOS technology; Logic circuits; Logic devices; Logic gates; Very large scale integration
• ISBN: 078031915X; 9780780319158
• DOI: 10.1109/ISCAS.1994.409262

This paper presents a BiCMOS dynamic multiplier, which is free from race and charge sharing problems, using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit. Based on a 1 /spl mu/m BICMOS technology, a 1.5 V 8/spl times/8 multiplier designed, shows a 2.3/spl times/ improvement in speed as compared to the CMOS static one.< >