Accelerator-Aware Computation Offloading Under Timing Constraints

• Published in: 2024 International Conference on Computing, Networking and Communications (ICNC) pp. 706 - 710
• Main Authors: Latzko, Vincent, Vielhaus, Christian, Mehrabi, Mahshid, Fitzek, Frank H. P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 19-02-2024
• Subjects: Artificial neural networks; Computation Offloading; Heterogeneous Computing; Machine learning; Multi-access edge computing; System-on-chip; Technological innovation; Timing; Vectors
• DOI: 10.1109/ICNC59896.2024.10556064
• EISSN: 2473-7585

The rise of chiplets in personal and high performance computing is mirrored in System on Chip (SOC) in mobile devices. Both paradigms allow vendors and designers to integrate dedicated circuitry for accelerating computation. Implementations like cryptographic or vector engines are well known, and nowadays Machine Learning (ML) blocks are often included to accelerate Deep Neural Network (DNN) inference. The shift toward diverse device architectures, as exemplified by RISC-V, is poised to gain momentum. The widespread integration of accelerators in smartphones, tablets, SoCs, and dedicated server systems, is opening up exciting new innovations. In this short paper we present computation offloading for specific workloads in the framework of Multi-Access Edge Computing (MEC) and energy optimisation. We honour inter-task dependency through use of a Directed Acyclic Graph (DAG). Our system model with multiple mobile users, Device-to-Device (D2D) links between User Equipments (UEs), and edge servers enables computational and communication cooperation. The system's energy efficiency is significantly improved by introducing accelerators to the UEs and the MEC. We study the capabilities of the devices (accelerators) and propose an effective solution.