An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor

• Published in: 2006 International Conference on Field Programmable Logic and Applications pp. 1 - 4
• Main Authors: Miyata, M., Tsuchiya, H., Shibata, Y., Oguri, K.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2006
• Subjects: Automata; Digital arithmetic; Fixed-point arithmetic; Galois fields; National electric code; Parallel processing; Phase locked loops; Polynomials; Switches; Tiles
• ISBN: 9781424403127; 142440312X
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2006.311291

Dynamically reconfigurable processor (DRP) released by NEC Electronics is expected to have potential for high degree of parallel processing. Applications for DRP are described in C language, and parallelism in the source code is automatically extracted by a compiler. On the other hand, it is also important to optimize descriptions so that the potential performance of the device is effectively brought out. In this paper, arithmetic algorithms and an optimized coding technique to efficiently implement applications with multi-cycled arithmetic functions on DRP are discussed, focusing on the required number of the states. In this technique, the same kind of multi-cycled functions are aggregated into single functions, and arithmetic algorithms whose behavior is steady on operand values are utilized. The effects of the technique are evaluated with fixed-point arithmetic functions and polynomial arithmetic functions over a finite field, showing 2.68~3.09 times performance improvement without large increase in the number of states nor severe degradation of the frequency