Delay management for programmable video signal processors

Delay management for programmable video signal processors

We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a dela...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings European Design and Test Conference. ED & TC 97 pp. 126 - 133
Main Authors: Smeets, M.L.G., Aarts, E.H.L., Essink, G., de Kock, E.A.
Format: Conference Proceeding
Language:English
Published: IEEE 1997
Subjects:
Delay
Job shop scheduling
Memory management
Resource management
Signal analysis
Signal mapping
Signal processing
Signal processing algorithms
Streaming media
Video signal processing
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Abstract We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms.
AbstractList We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms.
Author Essink, G.
Aarts, E.H.L.
Smeets, M.L.G.
de Kock, E.A.
Author_xml – sequence: 1
  givenname: M.L.G.
  surname: Smeets
  fullname: Smeets, M.L.G.
  organization: Philips Res., Eindhoven, Netherlands
– sequence: 2
  givenname: E.H.L.
  surname: Aarts
  fullname: Aarts, E.H.L.
– sequence: 3
  givenname: G.
  surname: Essink
  fullname: Essink, G.
– sequence: 4
  givenname: E.A.
  surname: de Kock
  fullname: de Kock, E.A.
BookMark eNotj0tLw0AUhS9awbZ2L67yBxLnztzMYylpfUDBTV2XaXMnRPIoM0XovzdSz-YsDhy-bwGzYRwY4BFFgSjc82a9qwp0zhSllYrKG5hLZUyulVS3sBAWrTbGaprBHIXWOZJw97BK6VtMcYRUlnNwa-78Jev94BvueThnYYzZKY5N9H3vDx1nP23NY5baZvDd33LklMaYHuAu-C7x6r-X8PW62VXv-fbz7aN62eatJHnO0aqDJibH8hiUx8DKlhMPTQzIgWpiGaRmK2sjUE9uZGuSRM6a2pBXS3i6_rbMvD_Ftvfxsr9Kq1_z20l0
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/EDTC.1997.582345
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library Online
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library Online
  url: http://ieeexplore.ieee.org/Xplore/DynWel.jsp
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISSN 2377-6323
EndPage 133
ExternalDocumentID 582345
GroupedDBID 6IE
6IK
6IL
AAJGR
ADZIZ
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
CHZPO
IPLJI
OCL
RIE
RIL
RNS
ID FETCH-LOGICAL-i242t-183b64e49e2cf3a1fe38506640091ef4d4e2f26e82d701611048d4244987d74a3
IEDL.DBID RIE
ISBN 0818677864
9780818677861
ISSN 1066-1409
IngestDate Wed Jun 26 19:22:41 EDT 2024
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i242t-183b64e49e2cf3a1fe38506640091ef4d4e2f26e82d701611048d4244987d74a3
PageCount 8
ParticipantIDs ieee_primary_582345
PublicationCentury 1900
PublicationDate 19970000
PublicationDateYYYYMMDD 1997-01-01
PublicationDate_xml – year: 1997
  text: 19970000
PublicationDecade 1990
PublicationTitle Proceedings European Design and Test Conference. ED & TC 97
PublicationTitleAbbrev EDTC
PublicationYear 1997
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0000941455
ssj0000558306
Score 1.27113
Snippet We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The...
SourceID ieee
SourceType Publisher
StartPage 126
SubjectTerms Delay
Job shop scheduling
Memory management
Resource management
Signal analysis
Signal mapping
Signal processing
Signal processing algorithms
Streaming media
Video signal processing
Title Delay management for programmable video signal processors
URI https://ieeexplore.ieee.org/document/582345
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ25T8MwFMYt2gkWoBRxywOr29jxOfcQE0KiSGxVYr9IoLapegz97_GRFpBY2JIsdmJZz3nv-34PoUeqwQdpvwJgqSNcVRXRzEqSM5NZLbQULjaxfVXP73o44nvOdvTCAEAUn0EvXMZavqvtNqTK-kKznIsWaimjk1XrkE7JhNB5UzD8TIK5gOCOtU4pScA6Rfpj5LdpyRv2zv6e7iuYmemPhpNBMPGpXhrvV9-VGHbGp_-a8Bnqftv38MshMJ2jI1h00MkP8uAFMkOYFTs8P4hfsD-84kasNQ92KhwMejUO-o5ihpfJT1Cv1l30Nh5NBk-k6aJAPnz43RC_Z0vJgRtgtsoLWkEeKHXSb15DoeKOA6uYBM2cCuc__3-mXbC_Ga2c4kV-idqLegFXCGemLEtLQRShGClEQYucQ1YqaQ1llb1GnfANpssEypim17_58-ktOk4k2JDNuEPtzWoL96i1dtuHuLJf5Oeaxw
link.rule.ids 310,311,782,786,791,792,798,4054,4055,27934,54768
linkProvider IEEE
linkToHtml http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlZ27T8MwEMYtWgZgAUoRbzywpo0dP-e2qIhSIVEktiqxLxKobao-Bv57bCctILGwJVnysKy73H3f7xC6IwpckHYrAIbYiMk8jxQ1Ikqojo3iSnAbhti-yOGb6vbYhrMdvDAAEMRn0PKHoZdvC7P2pbI2VzRhvIZ2OXNZcmnW2hZUYs5VUrUMP0rJnIdwh26nEJEHOwX-YyC4KcEq-s7mnGx6mLFu97qjjrfxyVZ5x1-TV0LguT_81yMfoea3gQ8_b0PTMdqBWQMd_GAPniDdhUn6iadb-Qt26Suu5FpTb6jC3qJXYK_wSCd4XjoKisWyiV7ve6NOP6rmKETvLgCvIrdrM8GAaaAmT1KSQ-I5dcJtX00gZ5YBzakARa30GaD7Q1PWG-C0klayNDlF9VkxgzOEY51lmSHAU9-O5DwlacIgzqQwmtDcnKOG_wbjeYnKGJevf_Hn1Vu01x89DcaDh-HjJdovubC-tnGF6qvFGq5RbWnXN2GVvwBHbZ4Z
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+European+Design+and+Test+Conference.+ED+%26+TC+97&rft.atitle=Delay+management+for+programmable+video+signal+processors&rft.au=Smeets%2C+M.L.G.&rft.au=Aarts%2C+E.H.L.&rft.au=Essink%2C+G.&rft.au=de+Kock%2C+E.A.&rft.date=1997-01-01&rft.pub=IEEE&rft.isbn=9780818677861&rft.issn=1066-1409&rft.eissn=2377-6323&rft.spage=126&rft.epage=133&rft_id=info:doi/10.1109%2FEDTC.1997.582345&rft.externalDocID=582345
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1066-1409&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1066-1409&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1066-1409&client=summon