Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

• Published in: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) pp. 1122 - 1125
• Main Authors: Jourdain, A., Buisson, T., Phommahaxay, A., Redolfi, A., Thangaraju, S., Travaly, Y., Beyne, E., Swinnen, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2011
• Subjects: Copper; Nails; Passivation; Silicon; Three dimensional displays; Through-silicon vias
• ISBN: 1612844979; 9781612844978
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2011.5898650

Among the many 3D technology options that are being explored today, the 3D-stacked IC approach has become a mature and economically viable technology and provides the highest density for 3D interconnects to date. One approach for IC stacking pursued by imec is the integration of Through Silicon Vias with extreme wafer thinning and backside processing on full CMOS wafers. This has been successfully demonstrated for the first time in a 300 mm production line, and the compatibility of thin wafer handling with backside processing has been evaluated.