Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and...

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Published in:2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS) pp. 1 - 4
Main Authors: Dae Seok Byeon, Chi-Weon Yoon, Hyun-Kook Park, Yong-Kyu Lee, Hyo-Jin Kwon, Yeong-Taek Lee, Ki-Sung Kim, Yong-Yeon Joo, In-Gyu Baek, Young-Bae Kim, Jeong-Dal Choi, Kye-Hyun Kyung, Jeong-Hyuk Choi
Format: Conference Proceeding
Language:English
Published: IEEE 01-10-2014
Subjects:
3D-Stack
Capacitance
Cross-point
Emerging memory
High density
Multi-bit cell
NAND Application
ReRAM
Resistive switching
Scaling limit
Surges
Switches
Write Disturbance
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Abstract In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.
AbstractList In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.
Author Yong-Yeon Joo
Hyo-Jin Kwon
Chi-Weon Yoon
Young-Bae Kim
Jeong-Hyuk Choi
Hyun-Kook Park
Yeong-Taek Lee
Ki-Sung Kim
Dae Seok Byeon
In-Gyu Baek
Yong-Kyu Lee
Jeong-Dal Choi
Kye-Hyun Kyung
Author_xml – sequence: 1
  surname: Dae Seok Byeon
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  surname: Chi-Weon Yoon
  fullname: Chi-Weon Yoon
  organization: Samsung Electron., Hwasung, South Korea
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  surname: Hyun-Kook Park
  fullname: Hyun-Kook Park
  organization: Samsung Electron., Hwasung, South Korea
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  surname: Yong-Kyu Lee
  fullname: Yong-Kyu Lee
  organization: Samsung Electron., Hwasung, South Korea
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  surname: Hyo-Jin Kwon
  fullname: Hyo-Jin Kwon
  organization: Samsung Electron., Hwasung, South Korea
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  surname: Yeong-Taek Lee
  fullname: Yeong-Taek Lee
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  organization: Samsung Electron., Hwasung, South Korea
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  surname: Yong-Yeon Joo
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  organization: Samsung Electron., Hwasung, South Korea
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  surname: In-Gyu Baek
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  organization: Samsung Electron., Hwasung, South Korea
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  surname: Young-Bae Kim
  fullname: Young-Bae Kim
  organization: Samsung Electron., Hwasung, South Korea
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  surname: Jeong-Dal Choi
  fullname: Jeong-Dal Choi
  organization: Samsung Electron., Hwasung, South Korea
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  surname: Kye-Hyun Kyung
  fullname: Kye-Hyun Kyung
  organization: Samsung Electron., Hwasung, South Korea
– sequence: 13
  surname: Jeong-Hyuk Choi
  fullname: Jeong-Hyuk Choi
  organization: Samsung Electron., Hwasung, South Korea
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Snippet In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test...
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SubjectTerms 3D-Stack
Capacitance
Cross-point
Emerging memory
High density
Multi-bit cell
NAND Application
ReRAM
Resistive switching
Scaling limit
Surges
Switches
Write Disturbance
Title Disturbance-suppressed ReRAM write algorithm for high-capacity and high-performance memory
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