100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array

• Published in: 2015 IEEE 11th International Conference on ASIC (ASICON) pp. 1 - 4
• Main Authors: Wang Jingjing, Xu Rongjin, Chen Chixiao, Ye Fan, Xu Jun, Ren Junyan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-11-2015
• Subjects: Capacitance; Capacitors; Clocks; Layout; Logic arrays; Power demand; Quantization (signal)
• ISBN: 9781479984831; 1479984833
• ISSN: 2162-755X
• DOI: 10.1109/ASICON.2015.7517107

This paper presents a low power 9-bit 100MS/s successive approximation register analog-to-digital converter (SAR ADC) due to the custom capacitor array. In this capacitor array, a brand-new 3-D 1-fF MOM unit capacitor is used as basic capacitor cell. A beneficial improvement to capacitor array structure makes some difference too. The design is fabricated in TSMC IP9M 65nm LP CMOS technology. At the same sampling rates of 100MS/s, the layout simulation of proposed SAR ADC achieves an ENOB of 8.54bit, an SNDR of 53.15dB, an SFDR of 63.14dB and power consumption of 0.43mW under Nyquist sampling. The FOM of the SAR ADC is low to 8.63fJ/conv.