A compact low-power eDRAM-based NoC buffer

• Published in: 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) pp. 116 - 121
• Main Authors: Cheng Li, Ampadu, Paul
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2015
• Subjects: area-efficient; Benchmark testing; buffer; Delays; embedded DRAM; low-power; Network-on-Chip; Pipelines; Random access memory; router; Switches; Tornadoes; Transistors
• DOI: 10.1109/ISLPED.2015.7273500

Whereas buffers significantly impact Network-on-Chip (NoC) performance, they also account for up to 75% and nearly 50% of NoC router area and power respectively. Traditionally, SRAM has been used as an area and power efficient implementation of the router buffer. However, motivated by the smaller size and lower-power potential of planar embedded DRAM (eDRAM), we implement the router buffer using a 3T NMOS eDRAM for improved power and area efficiency. We demonstrate that the lifetime of flits stalled in the NoC router buffer is much shorter than the retention time of currently available eDRAM. This observation allows us to make the appropriate trade-off in size and sense-amplifier complexity to meet requirements of power and performance. A low-overhead need-based refresh mechanism is further explored. With a conservative buffer design using 65nm CMOS technology, our method reduces buffer area by up to 52% and power by 43%, while maintaining performance similar to a SRAM-based buffer. In a NoC router with 128-bit channel width, we achieve 26% and 11% reduction of total router area and power respectively. We conclude that eDRAM-based buffer is a power and area efficient alternative to SRAM-based buffer for NoC router design.