High speed single phase SOGI-PLL with high resolution implementation on an FPGA

• Published in: 2015 IEEE 24th International Symposium on Industrial Electronics (ISIE) pp. 1004 - 1009
• Main Authors: Cossutta, Pablo, Raffo, Santiago, Cao, Andres, Ditaranto, Francisco, Aguirre, Miguel Pablo, Valla, Maria Ines
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01-06-2015
• Subjects: Algorithm design and analysis; Algorithms; Digital signal processing; Distortion; Field programmable gate arrays; Hardware; Harmonic analysis; Phase locked loops; Sampling; Synchronism; Synchronization
• ISSN: 2163-5137; 2163-5145
• DOI: 10.1109/ISIE.2015.7281609

Every power converter needs a precise synchronization method to be able to connect to the utility grid. The synchronization impacts directly on the performance of the converter. Synchronization algorithms are often based on the well known Synchronous Reference Frame Phase Locked Loop (SRF-PLL). These are usually implemented in software on Digital signal Processors (DSP) or Microcontrollers and the maximum sample rate that can be achieved is limited by the hardware used. In this paper a simple and highly effective Field Programmable Gate Array (FPGA) implementation of a Phase Locked Loop (PLL) algorithm based on a Second Order Generalized Integrator PLL (SOGI-PLL) with a high sampling frequency of 500 kHz and 16 bit resolution is presented in detail. Design time is drastically reduced by the use of a fast-prototype high-level synthesis tool without the need of any Hardware Description Language (HDL) code. Both simulation and experimental results on a Xilinx FPGA show an excellent behavior even against severe distortion and frequency or phase steps in the input voltage.