Energy efficiency of FPGAs and programmable processors for matrix multiplication

• Published in: 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings pp. 422 - 425
• Main Authors: Scrofano, R., Seonil Choi, Prasanna, V.K.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY IEEE 2002
• Subjects: Applied sciences; Clocks; Computer science; Computer systems; Delay; Design. Technologies. Operation analysis. Testing; Digital signal processing; Digital signal processors; Electronics; Energy consumption; Energy efficiency; Exact sciences and technology; Field programmable gate arrays; Hardware; Integrated circuits; Integrated circuits by function (including memories and processors); Power engineering and energy; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal processing; Performance evaluation; Boarded computer; Energy consumption; Power consumption; Energetic efficiency; Integrated circuit; Signal processing; Field programmable gate array; Digital signal processor
• ISBN: 0780375742; 9780780375741
• DOI: 10.1109/FPT.2002.1188725

Advances in their technologies have positioned FPGAs and embedded processors to compete with digital signal processors (DSPs). In this paper, we evaluate the performance in terms of both latency and energy-efficiency of FPGAs, embedded processors, and DSPs in multiplying two n /spl times/ n matrices. As specific examples, we have chosen a representative of each type of device. Our results show that the FPGAs can multiply two n /spl times/ n matrices with both lower latency and lower energy consumption than the other two types of devices. This makes FPGAs the ideal choice for matrix multiplication in signal processing applications.