Towards Improved Nanosheet-Based Complementary Field Effect Transistor (CFET) Performance Down to 42nm Contacted Gate Pitch

• Published in: 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) pp. 1 - 3
• Main Authors: Chiarella, T., Matagne, P., Mertens, H., Hosseini, M., Zhou, X., Eyben, P., Arimura, H., Gupta, A., Richard, O., Drijbooms, C., Caluwaerts, R., Horiguchi, N., Mitard, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 03-03-2024
• Subjects: Contacts; Doping; Field effect transistors; Logic gates; Performance evaluation; Resistance; Shape
• DOI: 10.1109/EDTM58488.2024.10512269

This work provides keys for optimizing nanosheet-based monolithic Complementary Field-Effect Transistors below 50nm gate pitch, relevant to industry "sub-nm" nodes. The impact of Source/Drain epitaxial growth, trench contact size, junction design and gate pitch on device performance are reviewed for top and bottom devices demonstrating electrically functional 42nm gate pitch devices. TCAD, calibrated to target DUT's, depicts up to 50% performance boost at low contact resistivity and high S/D doping, paving the way for next-generation CFET devices.