H-GCN: A Graph Convolutional Network Accelerator on Versal ACAP Architecture

• Published in: 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL) pp. 200 - 208
• Main Authors: Zhang, Chengming, Geng, Tong, Guo, Anqi, Tian, Jiannan, Herbordt, Martin, Li, Ang, Tao, Dingwen
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2022
• Subjects: Adaptive systems; Computer architecture; Convolutional neural networks; Engines; Graph convolutional network; Graph neural networks; Heterogeneous acceleration; Logic arrays; Machine learning; Sparse matrices; Sparse systolic tensor array; Systolic arrays; Tensors; Versal Adaptive Compute Acceleration Platform
• ISSN: 1946-1488
• DOI: 10.1109/FPL57034.2022.00040

Graph Neural Networks (GNNs) have drawn tremendous attention due to their unique capability to extend Machine Learning (ML) approaches to applications broadly-defined as having unstructured data, especially graphs. Compared with other Machine Learning (ML) modalities, the acceleration of Graph Neural Networks (GNNs) is more challenging due to the irregularity and heterogeneity derived from graph typologies. Existing efforts, however, have focused mainly on handling graphs' irregularity and have not studied their heterogeneity. To this end we propose H-GCN, a PL (Programmable Logic) and AIE (AI Engine) based hybrid accelerator that leverages the emerging heterogeneity of Xilinx Versal Adaptive Compute Acceleration Platforms (ACAPs) to achieve high-performance GNN inference. In particular, H-GCN partitions each graph into three subgraphs based on its inherent heterogeneity, and processes them using PL and AIE, respectively. To further improve performance, we explore the sparsity support of AIE and develop an efficient density-aware method to automatically map tiles of sparse matrix-matrix multiplication (SpMM) onto the systolic tensor array. Compared with state-of-the-art GCN accelerators, H-GCN achieves, on average, speedups of 1.1~2.3x.