An Ultra-Fast Parallel Prefix Adder

• Published in: 2019 IEEE 26th Symposium on Computer Arithmetic (ARITH) pp. 125 - 134
• Main Authors: Pandey, Kumar Sambhav, B, Dinesh Kumar, Goel, Neeraj, Shrimali, Hitesh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2019
• Subjects: adder recurrence relations; Adders; Computer architecture; Digital arithmetic; Logic gates; Microprocessors; Parallel prefix adders; Terminology; Topology
• ISSN: 2576-2265
• DOI: 10.1109/ARITH.2019.00034

Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26% improvement.