A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture

• Published in: 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID) pp. 207 - 212
• Main Authors: Raveendran, Aneesh, Jean, Sandra, Mervin, J., Vivian, D., Selvakumar, David
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-01-2020
• Subjects: Floating Point Unit; Fused Divide-Square Root; IEEE-754; POSIT Arithmetic Circuits; Type-III Unum POSIT
• ISSN: 2380-6923
• DOI: 10.1109/VLSID49098.2020.00053

In modern computing systems and devices, Floating-Point Unit (FPU) plays a significant role on performance-oriented, compute-intensive, Machine Learning/AI related applications. Currently two types of representations for floating-point numbers have been followed, viz. conventional IEEE-754-2008 and recently proposed Type-III Unum POSIT number which has wider dynamic range. Most of the modern processors have FPU as co-processor in order to improve the floating-point performance. Among various FP computations, division and square-root are generally the least-likely performed operations. These hardware operations are typically expensive in-terms of area, speed and power. The overall performance of floating-point division and square-root unit can be significantly affected by the chosen algorithm and the architecture of the implementation. A novel, modified, non-restoring algorithm and a POSIT iterative/pipelined architecture which performs fused division and square-root operation in a single unit, is proposed in this research work. For parameterized POSIT, a one-bit, modified, non-restoring fused division and square-root unit is the core component and can be reused/configured for different exponent and mantissa sizes. We have developed an iterative/pipelined parameterized POSIT fused division and square-root module using Verilog HDL and implemented, validated on Xilinx Virtex UltraScale VCU108 FPGA board (544 LUTs and achieved a throughput of 400 Mega POSIT operations per second). The results have been analyzed and compared in-terms of area-utilization and throughput with known published equivalent IEEE-754-2008 implementations and other POSIT divider units. The proposed design has less data-path delay, uses less hardware and achieves better throughput as compared to published results. The design has also been synthesized targeting SCL 180nm ASIC and achieved a throughput of 250 Mega POSIT operations per second.