Combining Topological & Physical Pattern Recognition To Enhance Memory Chip Reliability

Combining Topological & Physical Pattern Recognition To Enhance Memory Chip Reliability

The demand for both non-volatile (NAND) and volatile dynamic random access memory (DRAM) chips in processor and application-specific integrated circuit (ASIC) designs has grown tremendously in recent years, due largely to rapid advances in semiconductor technology coupled with the trending popularit...

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Bibliographic Details
Published in:2020 IEEE International Integrated Reliability Workshop (IIRW) pp. 1 - 4
Main Authors: Hany, Sherif, Byun, Sunsoo, Sarhan, Hossam, Medhat, Dina, ElRefaee, Mohamed, Jang, Jaehyun, Jeong, Baekryong, Choi, Hyunseung, Choi, Sunmi, Muirhead, Jonathan, Hogan, Matthew
Format: Conference Proceeding
Language:English
Published: IEEE 01-10-2020
Subjects:
Debugging
DRAM
electrical pattern
Fingers
geometrical pattern
Integrated circuit reliability
Layout
matching
Memory
memory robustness
NAND
Pattern matching
Reliability
Reliability engineering
reliability verification
sense amplifier
symmetry
topological pattern
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Summary:The demand for both non-volatile (NAND) and volatile dynamic random access memory (DRAM) chips in processor and application-specific integrated circuit (ASIC) designs has grown tremendously in recent years, due largely to rapid advances in semiconductor technology coupled with the trending popularity of low-power smart devices. This work demonstrates a proven automated reliability checking and debugging flow that combines electrical topologies with their geometrical patterns to ensure precise verification of reliability design rule compliance, especially for low-power high-speed applications using NAND/DRAM.
ISSN:2374-8036
DOI:10.1109/IIRW49815.2020.9312861