Board Level Solder Joint Reliability Design and Analysis of FOWLP

• Published in: 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) pp. 316 - 320
• Main Authors: Zhang, Xiaowu, Lau, Boon Long, Chen, Haoran, Han, Yong, Jong, Ming Chinq, Lim, Sharon Pei Siang, Lim, Simon Siak Boon, Wang, Xiaobai, Andriani, Yosephine, Liu, Songlin
• Format: Conference Proceeding
• Language: English
• Published: IEEE 02-12-2020
• Subjects: Creep; Packaging; Predictive models; Reliability; Semiconductor device reliability; Soldering; Strain
• DOI: 10.1109/EPTC50525.2020.9314996

This paper presents a comprehensive board level solder joint reliability study under thermal cycling (TC) loading by both numerical simulation and experimental test. TC profile is from −40°C to 125°C. In numerical simulation, both epoxy molding compound (EMC) and dielectric are modeled as viscoelastic materials. SAC is modeled as a creep material while the remaining materials are assumed to be elastic. The critical solder joint location predicted by modeling agrees well with the experimental result. Results show: (1) lower CTE PCB improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB CTE is reduced from 17 ppm/°C to 10ppm/°C; (2) thinned PCB thickness improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB thickness is reduced from 1.5 mm to 1 mm. Finally, life prediction model for solder joints of FOWLP has been successfully established as well.