Towards Highly Automated Machine-Learning-Empowered Monitoring of Motor Test Stands

• Published in: 2021 IEEE International Conference on Autonomic Computing and Self-Organizing Systems (ACSOS) pp. 120 - 130
• Main Authors: Botache, Diego, Bethke, Florian, Hardieck, Martin, Bieshaar, Maarten, Brabetz, Ludwig, Ayeb, Mohamed, Zipf, Peter, Sick, Bernhard
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2021
• Subjects: Deep Neuronal Networks; Failure Detection; FPGA Quantized Deep Neural Networks; Life estimation; Monitoring; Neural networks; Power demand; Predictive Maintenance; Sensors; Time factors; Time series analysis; Traction motors
• DOI: 10.1109/ACSOS52086.2021.00031

The development of new electric traction machines requires a complex process of experimentation due to the many factors that affect motor performance. Dedicated test benches, which are complex and vulnerable to failures during experiments, generate heterogeneous multivariate time series data collected by multiple sensors. Failures or anomalous states in these systems can slow down the development and testing process enormously. This article proposes a new and innovative approach to machine-learning-empowered monitoring and predictive maintenance for motor test benches. It allows to optimize the test process and reduce costly test bench downtime, with a self-improvement cycle to respond to new operation areas during run-time, integration of new components, continuous knowledge integration of human operators, autonomous parameter updating of machine-learning models, and hardware accelerated monitoring. Based on a first case study, we show that our procedure produces promising results based on the raw data for failure detection and failure type classification, representing an essential block of self-awareness in the system. A dedicated hardware-accelerated machine-learning online monitoring allows to meet critical time constraints and optimise power consumption. In a second case study, we demonstrate automated word-width reductions, which results in a smaller implementation of the network and reduce the needed memory bandwidth. All by keeping floating point accuracy and taking reconfigurable constant coefficient multiplication instead of generic multiplication into account.