Innovative Practice on Wafer Test Innovations

• Published in: 2020 IEEE 38th VLSI Test Symposium (VTS) p. 1
• Main Authors: Hu, Dyi-Chung, Hashimoto, Hirohito, Tseng, Li-Fong, Cheng, Ken Chau-Cheung, Shu-Min Li, Katherine, Wang, Sying-Jyan, Chen, Sean Y.-S., Chen, Jwu E, Liu, Clark, Huang, Andrew
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2020
• Subjects: Automatic test equipment; Costs; Measurement; Pattern recognition; Statistical analysis; Technological innovation; Very large scale integration
• ISSN: 2375-1053
• DOI: 10.1109/VTS48691.2020.9107619

Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.