A Hardware Generator of Two-Dimensional Cell- Averaging Constant False Alarm Rate Processors

• Published in: 2023 IEEE 33rd International Conference on Microelectronics (MIEL) pp. 1 - 4
• Main Authors: Petrovic, M. L., Milovanovic, V. M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-10-2023
• Subjects: Codes; Computer architecture; Data processing; Detectors; Generators; Hardware; Real-time systems
• ISSN: 2159-1679
• DOI: 10.1109/MIEL58498.2023.10315827

Two-dimensional constant false alarm rate (2D-CFAR) procedure is an indispensable part of radar signal processing for object detection in cluttered and noisy environments. A software implementation of this adaptive algorithm cannot achieve real-time data processing performance for many radar applications due to its computationally intensive nature. Besides the processing speed, another important feature of these detectors is their ability to adjust to different environments and weather conditions. Therefore, a parametrizable hardware design code generator of two-dimensional cell-averaging CFAR (2D-CA-CFAR) detectors with fully streaming input and output interfaces and a novel pipeline architecture that exploits a high level of parallelism is captured inside the Chisel hardware description language. The proposed hardware generator is designed in a modular fashion. It supports dynamic configuration options that include reference and guard window sizes, the radar data matrix (RDM) dimensions, as well as compile-time parameters such as input and output data types and widths and stream-out interface configuration. A range of representative 2D-CA-CFAR instances are implemented and mutually compared on a commercially available FPGA platform.