Construction of VHDL-AMS simulator in Matlab

Construction of VHDL-AMS simulator in Matlab

We describe the digital kernel implementation of the simulator S.A.M.S.A., a tool for the simulation of VHDL-AMS systems in Matlab/sup /spl trade//. The digital kernel was validated by simulating different systems. In particular we will show the simulation of a low-power multistage decimator for a w...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation pp. 113 - 117
Main Authors: Zorzi, M., Franze, F., Speciale, N.
Format: Conference Proceeding
Language:English
Published: IEEE 2003
Subjects:
Circuit simulation
Computer languages
Design automation
Engines
Kernel
Libraries
Mathematical model
MATLAB
Object oriented modeling
Wideband
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We describe the digital kernel implementation of the simulator S.A.M.S.A., a tool for the simulation of VHDL-AMS systems in Matlab/sup /spl trade//. The digital kernel was validated by simulating different systems. In particular we will show the simulation of a low-power multistage decimator for a wideband /spl Delta/-/spl Sigma/ analog to digital converter (ADC). This example was correctly simulated given the same results as other VHDL commercial tools.
ISBN:9780780381353
0780381351
DOI:10.1109/BMAS.2003.1249868