Physics based scalable MOSFET mismatch model for statistical circuit simulation

• Published in: 2007 IEEE Conference on Electron Devices and Solid-State Circuits pp. 1063 - 1066
• Main Authors: Lim, G.H., Zhou, X., Khu, K., Yoo, Y.K., Poh, F., See, G.H., Zhu, Z.M., Wei, C.Q., Lin, S.H., Zhu, G.J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2007
• Subjects: Circuit simulation; Circuit testing; CMOS technology; Coupling circuits; Monte Carlo methods; MOSFET circuits; Physics; Predictive models; Semiconductor device modeling; Voltage
• ISBN: 9781424406364; 1424406366
• DOI: 10.1109/EDSSC.2007.4450311

MOSFET mismatch model based on BSIM3v3 for a CMOS 0.13 μm technology using backward propagation of variance (BPV) methodology coupled with Pelgrom model basis was developed. Test structures were carefully designed for intrinsic MOSFET drain current mismatch characterisation under 4 different gate voltages that vary from weak to strong inversion for both linear and saturation regions. Monte Carlo MOSFET matched pair simulation using HSPICE was performed for model verification. The model was shown to be scalable for different biases and sizes and physically consistent in predicting the MOSFET mismatch in threshold voltage in linear and saturation regions.