Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology

• Published in: 2008 1st Microsystems and Nanoelectronics Research Conference pp. 181 - 184
• Main Authors: Bo Wang, Dianyong Chen, Bangli Liang, Kwasniewski, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2008
• Subjects: Circuit synthesis; CML; CMOS; CMOS digital integrated circuits; CMOS technology; deep-submicron (DSM); Design optimization; Digital circuits; Frequency; high-speed digital circuits; MOSFET circuits; nano-technology; Nanotechnology; Semiconductor device modeling; ultra-deep-submicron (UDSM); Voltage
• ISBN: 9781424429202; 142442920X
• DOI: 10.1109/MNRC.2008.4683408

This paper presents a biasing optimization technique for high-speed digital circuits design with advanced CMOS nanotechnology. Modern CMOS nanotechnology introduces several new problems in high-speed circuits design. As the fastest signal frequency components approach the peak transition frequency of the MOSFET, which depends heavily on the biasing voltage, the optimized biasing techniques become very important in high-speed circuits. Many trade-offs in the high-speed circuits need to be considered, and either power or headroom may be traded for higher speed. The optimized biasing technique is thoroughly analyzed first in this paper, and a typical high-speed CML circuit is designed based on this technique.