1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices

To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC d...

Full description

Bibliographic Details

Published in:	2007 IEEE Asian Solid-State Circuits Conference pp. 192 - 195
Main Authors:	Sangkwon Na, Woong Hwangbo, Jaemoon Kim, Seunghan Lee, Chong-Min Kyung
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-11-2007
Subjects:	Automatic voltage control Decoding Hardware IEC standards ISO standards Pipeline processing Solid state circuits Streaming media Throughput Video coding
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!