1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices

1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices

To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC d...

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Bibliographic Details
Published in:2007 IEEE Asian Solid-State Circuits Conference pp. 192 - 195
Main Authors: Sangkwon Na, Woong Hwangbo, Jaemoon Kim, Seunghan Lee, Chong-Min Kyung
Format: Conference Proceeding
Language:English
Published: IEEE 01-11-2007
Subjects:
Automatic voltage control
Decoding
Hardware
IEC standards
ISO standards
Pipeline processing
Solid state circuits
Streaming media
Throughput
Video coding
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Summary:To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC decoder architecture can support CIF(352x288) 30 fps videos at 6MHz with 1.8 mW @ 1.65 V, implemented in 0.18 mum technology.
ISBN:1424413591
9781424413591
DOI:10.1109/ASSCC.2007.4425763