Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET

• Published in: 2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) pp. 1 - 4
• Main Authors: Turker, Didem, Upadhyaya, Parag, Im, Jay, Stanley Chen, Frans, Yohan, Ken Chang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2017
• Subjects: CMOS technology; Field programmable gate arrays; FinFETs; Internetworking; NRZ; PAM4; Receivers; SerDes; Transceivers; Wideband; Wireline Transceivers
• ISSN: 2374-8443
• DOI: 10.1109/CSICS.2017.8240462

This paper describes circuit techniques for high speed transceivers used in FPGA applications. Three architectures in 16nm FinFET encompassing NRZ and PAM4 modulation are discussed. First, a 0.5-32.75Gb/s flexible reach NRZ transceiver achieves BER <;10 -15 over 30dB loss backplane at 32.75Gb/s while consuming 577mW. It features 3 stages of CTLE including a gain segmented AGC, 15 tap DFE, 2 LC PLLs and a ring PLL to offer continuous frequency range over both long and short reach channels. Secondly, a 40-56Gb/s PAM4 receiver with analog front end achieves BER<;10 -10 over a 10dB loss channel at 56Gb/s with crosstalk and consumes 230mW. It uses a direct feedback 10-tap DFE for power efficiency. Lastly, a 40-56Gb/s ADC based PAM4 transceiver achieves BER<;10 -8 over a 31dB loss channel at 56Gb/s with crosstalk. It features a 4 stage CTLE, an 8-bit SAR ADC, a 14 tap FFE and a 1 tap DFE to achieve long reach operation.