Simulation-based memory dependence checker for CGRA-mapped code verification

• Published in: 2014 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1235 - 1238
• Main Authors: Heejun Shim, Soojung Ryu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2014
• Subjects: CGRA; Computer architecture; History; Indexes; Memory Dependence; Pipeline processing; Processor scheduling; Registers; Software; Verification
• ISSN: 0271-4302; 2158-1525
• DOI: 10.1109/ISCAS.2014.6865365

In a coarse-grained reconfigurable array (CGRA) architecture, software pipelining is primarily used to improve performance by exploiting loop-level parallelism (LLP). In this technique, the loop-carried memory dependence in user code prevents high parallelism, and it is difficult to be detected. In this paper, we propose a simulation-based memory dependence checker, which is used in the verification of CGRA-mapped code. We use as a reference the memory access behavior of the sequential processor and compare it to that of the CGRA-mapped code. Although it cannot guarantee perfect verification of memory dependence violations, our approach is useful by guiding the programmer to modify the source code. When a memory dependence violation is detected, our approach provides debugging information from the sequential compiled code. Moreover, our checker is implemented in the register transfer level; it enables verification time reduction and the testing of the CGRA-mapped code with a large test input stream in FPGA or ASIC implementations.