Design-for-test and test time optimization for 3D SOCs

• Published in: 2017 IEEE International Test Conference (ITC) pp. 1 - 10
• Main Authors: Roy, Surajit Kumar, Giri, Chandan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2017
• Subjects: Algorithm design and analysis; Optimization; Testing; Three-dimensional displays; Through-silicon vias; Two dimensional displays
• ISSN: 2378-2250
• DOI: 10.1109/TEST.2017.8242082

Three dimensional (3D) integration based on through-Silicon-Via (TSV) is currently evolving as an area of great interest in modern semiconductor industry. 3D integration provides higher performance, bandwidth and lower power consumption. But due to scaling in technology features these chips are more complex. Hence, testing of these 3D integrated circuits (ICs) is a challenging task. Effective test architecture design and optimization techniques are essential to minimize the manufacturing test cost. This paper addresses test architecture optimization and Design-for-Test (DfT) for 3D ICs. We design test wrapper for 3D SOC using minimum number of TSVs. Heuristic algorithms are proposed to minimize test time for 3D SOC. Also, TSVs for test access is limited due to small chip area. To address this issue, algorithms are proposed to minimize overall test time considering all possible partial stacks and complete stack for 3D IC with hard dies under TSV constraint. We next describe strategies to identify faulty TSVs in reduced test time. Finally, we present techniques for recovery of those faulty TSVs in 3D IC.