A Practical Method for Testing High-Speed Networking Hardware Architectures

• Published in: 2009 Fifth International Conference on Networking and Services pp. 122 - 130
• Main Authors: Pejovic, V., Bojanic, S., Carreras, C., Badii, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2009
• Subjects: Application specific integrated circuits; Costs; Ethernet networks; Field programmable gate arrays; FPGA; Hardware; High-speed networks; high-speed prototyping; Logic testing; networking hardware; Phased arrays; Prototypes; re-configurability; System testing; Test; testability platform
• ISBN: 9781424436880; 1424436885
• DOI: 10.1109/ICNS.2009.50

This paper deals with the key issues encountered in testing during the development of high-speed networking hardware systems by documenting a practical method for "real-life like" testing. The proposed method is empowered by modern and commonly available Field Programmable Gate Array (FPGA) technology. Innovative application of standard FPGA blocks in combination with reconfigurability are used as a back-bone of the method. A detailed elaboration of the method is given so as to serve as a general reference. The method is fully characterised and compared to alternatives through a case study proving it to be the most efficient and effective one at a reasonable cost.