Simple self-aligned air-gap interconnect process with Cu/FSG structure

• Published in: Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) pp. 68 - 70
• Main Authors: Noguchi, J., Fujiwara, T., Sato, K., Nakamura, T., kubo, M., Uno, S., Ishikawa, K., Saito, T., Konishi, N., Yamada, Y., Tamaru, T.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Air gaps; Capacitance; Chemicals; CMOS process; CMOS technology; Delamination; Delay; Dielectric constant; Large scale integration; Silicon carbide
• ISBN: 9780780377974; 0780377974
• DOI: 10.1109/IITC.2003.1219715

A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.