Multicore processor cluster based sleep transistor sizing considering delay profile

• Published in: 2009 IEEE 8th International Conference on ASIC pp. 654 - 657
• Main Authors: Huang Huang, Fan, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-10-2009
• Subjects: Adders; Circuit topology; Degradation; Delay effects; Low Power; Multicore; Multicore processing; Power dissipation; Slack Time; Sleep; Sleep Transistor; Switching circuits; Threshold voltage; Timing
• ISBN: 9781424438693; 1424438691; 1424438683; 9781424438686
• ISSN: 2162-7541; 2162-755X
• DOI: 10.1109/ASICON.2009.5351331

This paper proposed a novel method to size the sleep transistor by considering the slack time of the gates in non-critical path in delay profile. The circuit topology was considered to calculate the switching factor, which consequently gave us a more accurate estimation of gates' discharge current. We implemented our method on a 4-bit adder. The proposed switching factor calculation could provide a more accurate estimation of switching current. In consideration of the slack time based on the delay profile, the equivalent worst case discharge current can be reduced, so that the number and the total size of sleep transistors can be dramatically reduced. In theory, the size of sleep transistor can be saved by up to a factor of 3, depending upon the design. In this paper, we also extended the sleep transistor sizing techniques into general multicore architecture. As an example, we modeled nine cores in design. Each core is assumed with different speed degradation allowed to process work loads with various performance requirements. Thus, a balanced design between power dissipation and circuit performance can be maintained.