Variability-tolerant current-mode link design for NoC

• Published in: 2013 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM) pp. 131 - 136
• Main Authors: Gawish, Eman Kamel, El-Kharashi, M. Watheq, AbuElYazeed, M. F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2013
• Subjects: Adaptation models; Correlation; Current-mode interconnect; Delays; Floor-plan; Integrated circuit interconnections; Mathematical model; Networks-on-Chip; process variability; Receivers; Systematics
• ISSN: 1555-5798; 2154-5952
• DOI: 10.1109/PACRIM.2013.6625462

This paper proposes a statistical link design methodology for variability-tolerant current-mode interconnect applied for Networks-on-Chip links. The model takes into considerations the systematic and random effects of process variability. The model calculates the resistive, capacitive and device variations then uses it to calculate current variations of each NoC link in a floor-plan. Statistical link design proposes a current safe guard to keep signal integrity versus existing process variability sources. The proposed technique is tested using test cases of 4×4 meshes at 65 nm, 45 nm, 32 nm, 22nm, and 16 nm technologies. Results show that the received current variations at 16nm approach 30% of the total current at the link receiver. The current variations are increased by 100% as NoC mesh size scales from 4×4 to 16×16 at 45 nm. Comparing our statistical design to worst-case at 65 nm, we save up to 33 % of the total power cost compared to worst-case. The link failure probability is modeled to calculate the average NoC link failure rate. NoC with links designed to have statistical guard achieves low failure rate that is up to 3.7 % for 4×4 mesh.