New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A

• Published in: 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 1387 - 1390
• Main Authors: Kalyani Garimella, Lalitha M., Sudha Garimella, Sri R., Duda, Kevin, Fetzer, Eric
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2013
• Subjects: Adders; Delays; Equations; Hardware; Logic gates; Mathematical model
• DOI: 10.1109/MWSCAS.2013.6674915
• EISSN: 1558-3899
• ISSN: 1548-3746

Proposed innovation gives a faster, lower depth, lower power and lower area solution for addition. The paper describes two novel static gates developed for 4-bit Majority Carry Generate (MCG) and Majority Carry Propagate (MCP) operation in a single gate depth. Derivation of a novel 72-bit CL2A within 6 gate-depth, using MCG, MCP and a novel sparse5 (5×2 n ) algorithm with a variable sparse is described. Implementation of a novel 64-bit CL3A within 5 gate-depth, by extending CL2A with progressive sparse 1+3 0 + 3 1 + 3 2 +...3 n algorithm is described. Silicon evaluation of an 8-bit application for the CL2A is presented in 32nm. Post-layout results of 64-bit CL2A and 64-bit CL3A against Ling-Carry-select adder are presented in 14nm along with the advantages and limitations.