CD-SEM metrology evaluation of gate-all-around Si nanowire MOSFET with improved control of nanowire suspension by using a buried boron nitride etch-stop layer

• Published in: 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014) pp. 248 - 251
• Main Authors: Cohen, Guy M., Shi, Leathen, Bangsaruntip, Sarunya, Grill, Alfred, Neumayer, Deborah, Levi, Shimon, Weinberg, Yakov, Shoval, Ori, Adan, Ofer, Tzi, Maayan Bar, Conley, Amiad
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2014
• Subjects: 3D-CDSEM; Boron Nitride; Gate-all-around (GAA) nanowire MOSFETs SOI; Logic gates; Rough surfaces; Silicon; Surface treatment; Suspensions; Wires
• ISSN: 1078-8743; 2376-6697
• DOI: 10.1109/ASMC.2014.6847014

In this work, we report a new fabrication method of Si nanowires that enables an accurate control of the suspension gap underneath the Si wire. It is achieved by using SOI wafers with an embedded boron nitride (BN) etch-stop layer. Physical characterization of the Si wires was performed with a 3D-CDSEM, measurement results are compared with the process of record where conventional SOI wafers are used. Metrology measurements provide new insights on the effect of SEM induced charge in altering the buckling orientation of imaged Si wires.