The eDRAM based L3-cache of the BlueGene/L supercomputer processor node

• Published in: 16th Symposium on Computer Architecture and High Performance Computing pp. 18 - 22
• Main Authors: Ohmacht, M., Hoenicke, D., Haring, R., Gara, A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Arithmetic; Bandwidth; Computer architecture; Delay; Ethernet networks; High performance computing; Prefetching; Random access memory; Supercomputers; System-on-a-chip
• ISBN: 0769522408; 9780769522401
• ISSN: 1550-6533; 2643-3001
• DOI: 10.1109/SBAC-PAD.2004.40

BlueGene/L is a supercomputer consisting of 64K dual-processor system-on-a-chip compute nodes, capable of delivering an arithmetic peak performance of 5.6Gflops per node. To match the memory speed to the high compute performance, the system implements an aggressive three-level on-chip cache hierarchy for each node. The implemented hierarchy offers high bandwidth and integrated prefetching on cache hierarchy levels 2 and 3 to reduce memory access time. The integrated L3-cache stores a total of 4MB of data, using multibank embedded DRAM. The 1024 bit wide data port of the embedded DRAM provides 22.4GB/s bandwidth to serve the speculative prefetching demands of the two processor cores and the Gigabit Ethernet DMA engine.