Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule

Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule

This paper proposes an improved message passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are effi...

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Published in:2007 International Symposium on Integrated Circuits pp. 508 - 511
Main Authors: Xing Li, Abe, Y., Shimizu, K., Zhen Qiu, Ikenaga, T., Goto, S.
Format: Conference Proceeding
Language:English
Published: IEEE 01-09-2007
Subjects:
Decoding
Energy consumption
Error correction
Error correction codes
Frequency
Hardware
Message passing
Parallel processing
Parity check codes
Processor scheduling
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Abstract This paper proposes an improved message passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.
AbstractList This paper proposes an improved message passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.
Author Shimizu, K.
Ikenaga, T.
Goto, S.
Xing Li
Zhen Qiu
Abe, Y.
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  organization: Waseda Univ., Fukuoka
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  givenname: S.
  surname: Goto
  fullname: Goto, S.
  organization: Waseda Univ., Fukuoka
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Snippet This paper proposes an improved message passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing...
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StartPage 508
SubjectTerms Decoding
Energy consumption
Error correction
Error correction codes
Frequency
Hardware
Message passing
Parallel processing
Parity check codes
Processor scheduling
Title Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule
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