Cost-Efficient Partially-Parallel Irregular LDPC Decoder with Message Passing Schedule

• Published in: 2007 International Symposium on Integrated Circuits pp. 508 - 511
• Main Authors: Xing Li, Abe, Y., Shimizu, K., Zhen Qiu, Ikenaga, T., Goto, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2007
• Subjects: Decoding; Energy consumption; Error correction; Error correction codes; Frequency; Hardware; Message passing; Parallel processing; Parity check codes; Processor scheduling
• ISBN: 9781424407965; 1424407966
• ISSN: 2325-0631
• DOI: 10.1109/ISICIR.2007.4441910

This paper proposes an improved message passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.