FPGA based design of hierarchical self-test for surveillance system

FPGA based design of hierarchical self-test for surveillance system

This paper describes various measures that have been taken to facilitate self-test of surveillance system. The structure and working of hierarchical self-test at system level, subsystem level and chip level is presented. Experiments are performed to verify the design and the results suggest that the...

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Bibliographic Details
Published in:2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) pp. 405 - 408
Main Authors: Panwar, Adesh, Kumar, Satish, Singh, Jitesh Kumar
Format: Conference Proceeding
Language:English
Published: IEEE 01-05-2017
Subjects:
BIST
BITE
Built-in self-test
DFT
Field programmable gate arrays
FPGA
Maintenance engineering
Radar
Radio frequency
Timing
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Description
Summary:This paper describes various measures that have been taken to facilitate self-test of surveillance system. The structure and working of hierarchical self-test at system level, subsystem level and chip level is presented. Experiments are performed to verify the design and the results suggest that the proposed system is able to isolate and diagnose the faults of a complex system such as surveillance system.
DOI:10.1109/RTEICT.2017.8256627