Cache filtering techniques to reduce the negative impact of useless speculative memory references on processor performance

• Published in: 16th Symposium on Computer Architecture and High Performance Computing pp. 2 - 9
• Main Authors: Mutlu, O., Kim, H., Armstrong, D.N., Patt, Y.N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Bandwidth; Computer architecture; Filtering; Filters; High performance computing; Pollution; Prefetching
• ISBN: 0769522408; 9780769522401
• ISSN: 1550-6533; 2643-3001
• DOI: 10.1109/SBAC-PAD.2004.11

High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes bring data into the caches that are not needed by correct execution. This paper proposes the use of the first-level caches as filters that predict the usefulness of speculative memory references. With the proposed technique, speculative memory references bring data only into the first-level caches rather than all levels in the cache hierarchy. The processor monitors the use of the cache blocks in the first-level caches and decides which blocks to keep in the cache hierarchy based on the usefulness of cache blocks. It is shown that a simple implementation of this technique usually outperforms inclusive and exclusive baseline cache hierarchies commonly used by today's processors and results in IPC performance improvements of up to 9.2% on the SPEC2000 integer benchmarks.