Interconnect reliability prediction for wafer level packages (WLP) for temperature cycle and drop load conditions

• Published in: 2014 IEEE 64th Electronic Components and Technology Conference (ECTC) pp. 100 - 107
• Main Authors: Tong Cui, Syed, Ahmer, Keser, Beth, Alvarado, Rey, Xu, Steven, Schwarz, Mark
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2014
• Subjects: Finite element analysis; Mathematical model; Predictive models; Reliability; Soldering; Strain; Temperature measurement
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2014.6897273

Interconnect reliability of wafer level packages (WLP) is one of the major concerns because of the direct connection of die to board without any substrate interposer. The dominant failure modes due to temperature cycling and drop include cracks in bulk solder, crack at pad to IMC interface, and RDL cracking at UBM interface. A number of factors affect this reliability; such as UBM/Pad size, bump density, bump depopulation, and die size and thickness. In addition, WLPs come in different flavors (UBM vs. No UBM,) which also have implications on interconnect reliability. With increasing die size, it is becoming critical to investigate this reliability very early in the product design cycle using simulations. Although simulations are very helpful in performing relative comparison to investigate design options, their utility can be further enhanced by developing life prediction models to determine if a certain design will meet customer reliability requirements for the end use application. This paper discusses a finite element modeling based approach to establish such a life prediction model. Failure data on various test vehicles were collected using board level temperature cycle and drop test methods. This data covered a large range of WLP designs including various die sizes, bump pitches, bump densities, UBM/Pad sizes, fab nodes, and WLP structures. Each of these data points were then simulated using a detailed 3-D finite element modeling approach to compute strain energy density (SED) per cycle for temperature cycle conditions. Similarly, drop tests were simulated to determine drop damage parameters (Stress, Strain, Strain energy density) at various interfaces and RDL trace. The models incorporate every detail of package geometry including die size, solder bump dimensions from measurement, detailed structure below and above solder bump such as back end of line (BEOL), polymer layers, redistribution layers (RDL), UBM, and copper pad. Material properties were also measured of test boards to improve model accuracy and published creep constitutive equations were used for simulating non-linear behavior of solder joints due to temperature cycling and drop loading conditions. The values of damage parameters determined from finite element modeling were then plotted against the mean life (50% failure rate) to establish the fatigue life prediction model. A power law curve fitting with a correlation coefficient of greater than 95% resulted in fatigue life exponent of approximately -1 for solder fatigue, which is consistent with previous life prediction models. Since the intent was to use the model to predict first failures and 5% failure rate, Weibull analysis and test database was used to determine ratios of lower limits of 5% life at 90% confidence to mean life. The combined use of highly accurate finite element modeling and statistical analysis of test database provides greater confidence in predicting reliability and thus a useful tool for assessing and optimizing design very early in the design phase.