Bulk Linearization Techniques

• Published in: 2019 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1 - 5
• Main Authors: Arnaud, Alfredo, Puyol, Rafael, Hardy, Denisse, Miguez, Matias, Gak, Joel
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2019
• Subjects: bulk-degeneration; CMOS transistor; linearization
• ISBN: 9781728103976; 1728103975
• ISSN: 2158-1525
• DOI: 10.1109/ISCAS.2019.8702327

The use of the bulk terminal to enhance the linear properties of the MOS transistor is examined. Firstly, bulk-linearization of a MOS differential pair is presented, including harmonic distortion measurements. Then bulk-degeneration technique is extended to the triode region to implement large MOS pseudo-resistors. A new asymmetric bulk-modified composite MOS with an equivalent saturation voltage of several hundred mV is introduced, and a 150MΩ pseudo-resistor by stacking a few of these stages is presented. Finally, bulk-linearization of the MOS differential pair and the MOS resistor are combined to implement a 6.4nS transconductor with above 1V linear range, consuming only 6nA, improving the compromise between linear range and power consumption of previously reported small transconductance OTAs.